#
12ac51cd |
|
16-Mar-2024 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
usb: udc: dwc3: Fold dwc3_uboot_handle_interrupt into dm_usb_gadget_handle_interrupts The only call site of dwc3_uboot_handle_interrupt() is the dm_usb_gadget_handle_interrupts(), fold the former into the later. This makes dwc3_uboot_handle_interrupt() unavailable to be called from board code as well. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # vim3 Link: https://lore.kernel.org/r/20240317044357.547037-2-marek.vasut+renesas@mailbox.org Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> |
#
4d158980 |
|
16-Mar-2024 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
usb: udc: dwc3: Fold board dm_usb_gadget_handle_interrupts() into DWC3 gadget The dm_usb_gadget_handle_interrupts() has no place in board code. Move this into DWC3 driver. The OMAP implementation is special, add new weak dwc3_uboot_interrupt_status() function to decide whether DWC3 interrupt handling should be called, and override it in OMAP DWC3 code, to repair the special OMAP interrupt handling code until OMAP gets switched over to DM UDC proper. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # vim3 Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # qcom sdm845 Link: https://lore.kernel.org/r/20240317044357.547037-1-marek.vasut+renesas@mailbox.org Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> |
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> |
#
2caf974b |
|
01-Sep-2023 |
Marek Vasut <marex@denx.de> |
board: usb: Replace legacy usb_gadget_handle_interrupts() The usb_gadget_handle_interrupts() is no longer used anywhere, replace the remaining uses with dm_usb_gadget_handle_interrupts() which takes udevice as a parameter. Some of the UDC drivers currently ignore the index parameter altogether, those also ignore the udevice and have to be reworked. Other like the dwc3_uboot_handle_interrupt() had to be switched from index to udevice look up to avoid breakage. Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on khadas vim3 Signed-off-by: Marek Vasut <marex@denx.de> |
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> |
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
4835c737 |
|
12-May-2016 |
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> |
usb: dwc3: Correct datatype of base to unsigned long Correct type of varibale base to unsigned long as keeping it as int causes usb failures if MSB of the base address is set. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
27d3b89d |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: added an API to invoke irq handlers Since interrupt support is not present in u-boot, added an API to handle the interrupts in dwc3 core. This API can be polled to handle the interrupts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
793d347f |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
da0d9e42 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
include: dwc3-uboot: add a structure for populating platform data Added a structure to populate dwc3 core platform data. The board file should populate these platform data before invoking dwc3 driver. This will be removed once we have dwc3 driver adapted to use the driver model. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> |
#
2caf974b |
|
01-Sep-2023 |
Marek Vasut <marex@denx.de> |
board: usb: Replace legacy usb_gadget_handle_interrupts() The usb_gadget_handle_interrupts() is no longer used anywhere, replace the remaining uses with dm_usb_gadget_handle_interrupts() which takes udevice as a parameter. Some of the UDC drivers currently ignore the index parameter altogether, those also ignore the udevice and have to be reworked. Other like the dwc3_uboot_handle_interrupt() had to be switched from index to udevice look up to avoid breakage. Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on khadas vim3 Signed-off-by: Marek Vasut <marex@denx.de> |
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> |
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
4835c737 |
|
12-May-2016 |
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> |
usb: dwc3: Correct datatype of base to unsigned long Correct type of varibale base to unsigned long as keeping it as int causes usb failures if MSB of the base address is set. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
27d3b89d |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: added an API to invoke irq handlers Since interrupt support is not present in u-boot, added an API to handle the interrupts in dwc3 core. This API can be polled to handle the interrupts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
793d347f |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
da0d9e42 |
|
23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
include: dwc3-uboot: add a structure for populating platform data Added a structure to populate dwc3 core platform data. The board file should populate these platform data before invoking dwc3 driver. This will be removed once we have dwc3 driver adapted to use the driver model. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
2caf974b |
|
01-Sep-2023 |
Marek Vasut <marex@denx.de> |
board: usb: Replace legacy usb_gadget_handle_interrupts() The usb_gadget_handle_interrupts() is no longer used anywhere, replace the remaining uses with dm_usb_gadget_handle_interrupts() which takes udevice as a parameter. Some of the UDC drivers currently ignore the index parameter altogether, those also ignore the udevice and have to be reworked. Other like the dwc3_uboot_handle_interrupt() had to be switched from index to udevice look up to avoid breakage. Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on khadas vim3 Signed-off-by: Marek Vasut <marex@denx.de> |
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> |
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> |
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
4835c737 |
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12-May-2016 |
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> |
usb: dwc3: Correct datatype of base to unsigned long Correct type of varibale base to unsigned long as keeping it as int causes usb failures if MSB of the base address is set. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
27d3b89d |
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23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: added an API to invoke irq handlers Since interrupt support is not present in u-boot, added an API to handle the interrupts in dwc3 core. This API can be polled to handle the interrupts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
793d347f |
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23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
da0d9e42 |
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23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
include: dwc3-uboot: add a structure for populating platform data Added a structure to populate dwc3 core platform data. The board file should populate these platform data before invoking dwc3 driver. This will be removed once we have dwc3 driver adapted to use the driver model. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> |
#
dc18413a |
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25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
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25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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#
7bb62708 |
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25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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#
73ca0140 |
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06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
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#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
b34f8b5d |
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25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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#
7bb62708 |
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25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
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#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
dc18413a |
|
25-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add disable u2mac linestate check quirk This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
b34f8b5d |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_u2_freeclk_exists_quirk Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
7bb62708 |
|
25-May-2020 |
Frank Wang <frank.wang@rock-chips.com> |
usb: dwc3: add dis_enblslpm_quirk Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
73ca0140 |
|
06-May-2020 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: add dis_del_phy_power_chg_quirk Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Reference from below Linux commit, commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6dfb8a80 |
|
02-May-2020 |
Chunfeng Yun <chunfeng.yun@mediatek.com> |
usb: dwc3: use the phy bulk API to get phys Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
6b7ebff0 |
|
19-Nov-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: dwc3: Add phy interface for dwc3_uboot U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
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#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
d648a50c |
|
29-Nov-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
dwc3: move phy operation to core.c Those operations can be used for peripheral operation as well as host operation. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> # Conflicts: # drivers/usb/dwc3/core.c # drivers/usb/host/xhci-dwc3.c
|
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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4835c737 |
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12-May-2016 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
usb: dwc3: Correct datatype of base to unsigned long Correct type of varibale base to unsigned long as keeping it as int causes usb failures if MSB of the base address is set. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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27d3b89d |
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23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: added an API to invoke irq handlers Since interrupt support is not present in u-boot, added an API to handle the interrupts in dwc3 core. This API can be polled to handle the interrupts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
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793d347f |
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23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
dwc3: core: add support for multiple dwc3 controllers Added support for multiple dwc3 controllers. This gives uboot the capability to control multiple dwc3 controllers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
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da0d9e42 |
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23-Feb-2015 |
Kishon Vijay Abraham I <kishon@ti.com> |
include: dwc3-uboot: add a structure for populating platform data Added a structure to populate dwc3 core platform data. The board file should populate these platform data before invoking dwc3 driver. This will be removed once we have dwc3 driver adapted to use the driver model. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
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