#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7d2bf7c2 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
spi: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
1d70101a |
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24-May-2023 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: remove SPI_TX_BYTE handling Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
84855959 |
|
06-Apr-2023 |
Ilias Apalodimas <ilias.apalodimas@linaro.org> |
spi: synquacer: Silence uninitialized variable warnings When building with clang, the compiler compains with drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here val |= ((bus_width >> 1) << BUS_WIDTH); ^~~~~~~~~ drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning So initialize bus_width to 1 and add a warning if none of the configured modes matches Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f81aaa0b |
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17-May-2022 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: simplify tx completion checking There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
de9f2c9c |
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17-May-2022 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: DMSTART bit must not be set while transferring DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
88d50ed8 |
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17-May-2022 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: wait until slave is deselected synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
29d382b9 |
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17-May-2022 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: busy variable must be initialized before use "busy" variable is ORed without being initialized, must be zeroed before use. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
971a3442 |
|
04-Jun-2021 |
Jassi Brar <jaswinder.singh@linaro.org> |
spi: synquacer: Add HSSPI SPI controller driver for SynQuacer This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> |
#
7d2bf7c2 |
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01-May-2024 |
Tom Rini <trini@konsulko.com> |
spi: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
1d70101a |
|
24-May-2023 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: remove SPI_TX_BYTE handling Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
84855959 |
|
06-Apr-2023 |
Ilias Apalodimas <ilias.apalodimas@linaro.org> |
spi: synquacer: Silence uninitialized variable warnings When building with clang, the compiler compains with drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here val |= ((bus_width >> 1) << BUS_WIDTH); ^~~~~~~~~ drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning So initialize bus_width to 1 and add a warning if none of the configured modes matches Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f81aaa0b |
|
17-May-2022 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: simplify tx completion checking There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
de9f2c9c |
|
17-May-2022 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: DMSTART bit must not be set while transferring DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
88d50ed8 |
|
17-May-2022 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: wait until slave is deselected synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
29d382b9 |
|
17-May-2022 |
Masahisa Kojima <kojima.masahisa@socionext.com> |
spi: synquacer: busy variable must be initialized before use "busy" variable is ORed without being initialized, must be zeroed before use. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
971a3442 |
|
04-Jun-2021 |
Jassi Brar <jaswinder.singh@linaro.org> |
spi: synquacer: Add HSSPI SPI controller driver for SynQuacer This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> |
#
1d70101a |
|
24-May-2023 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: remove SPI_TX_BYTE handling Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
84855959 |
|
06-Apr-2023 |
Ilias Apalodimas <ilias.apalodimas@linaro.org> |
spi: synquacer: Silence uninitialized variable warnings When building with clang, the compiler compains with drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here val |= ((bus_width >> 1) << BUS_WIDTH); ^~~~~~~~~ drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning So initialize bus_width to 1 and add a warning if none of the configured modes matches Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f81aaa0b |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: simplify tx completion checking There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
de9f2c9c |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: DMSTART bit must not be set while transferring DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
88d50ed8 |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: wait until slave is deselected synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
29d382b9 |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: busy variable must be initialized before use "busy" variable is ORed without being initialized, must be zeroed before use. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
971a3442 |
|
04-Jun-2021 |
Jassi Brar <jaswinder.singh@linaro.org> |
spi: synquacer: Add HSSPI SPI controller driver for SynQuacer This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> |
#
84855959 |
|
06-Apr-2023 |
Ilias Apalodimas <ilias.apalodimas@linaro.org> |
spi: synquacer: Silence uninitialized variable warnings When building with clang, the compiler compains with drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here val |= ((bus_width >> 1) << BUS_WIDTH); ^~~~~~~~~ drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning So initialize bus_width to 1 and add a warning if none of the configured modes matches Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f81aaa0b |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: simplify tx completion checking There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
de9f2c9c |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: DMSTART bit must not be set while transferring DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
88d50ed8 |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: wait until slave is deselected synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
29d382b9 |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: busy variable must be initialized before use "busy" variable is ORed without being initialized, must be zeroed before use. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
971a3442 |
|
04-Jun-2021 |
Jassi Brar <jaswinder.singh@linaro.org> |
spi: synquacer: Add HSSPI SPI controller driver for SynQuacer This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> |
#
f81aaa0b |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: simplify tx completion checking There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
de9f2c9c |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: DMSTART bit must not be set while transferring DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
88d50ed8 |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: wait until slave is deselected synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
29d382b9 |
|
17-May-2022 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
spi: synquacer: busy variable must be initialized before use "busy" variable is ORed without being initialized, must be zeroed before use. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> |
#
971a3442 |
|
04-Jun-2021 |
Jassi Brar <jaswinder.singh@linaro.org> |
spi: synquacer: Add HSSPI SPI controller driver for SynQuacer This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> |
#
971a3442 |
|
04-Jun-2021 |
Jassi Brar <jaswinder.singh@linaro.org> |
spi: synquacer: Add HSSPI SPI controller driver for SynQuacer This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> |