#
d678a59d |
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18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c45973bc |
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01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
778f4eaa |
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27-Oct-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Add stm32mp2 support Add stm32mp2 compatible. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
1e94b46f |
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14-Sep-2023 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/printk.h from common header This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bff0d846 |
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27-Mar-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() For debug purpose, it should be useful to indicate the slew rate for each pins. Add ospeed register information for pins which are configured in either alternate function or gpio output. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
2c38f7c3 |
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30-Aug-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name Populate uc_priv->name[] with pinmux node's name in order to indicate the pinmuxing's name in case GPIO is configured in alternate. For example, for STM32 SoC's based platform, "gpio status" command output : before Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func GPIOZ5: func GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown After Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func i2c4-0 GPIOZ5: func i2c4-0 GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
cf1d0fd4 |
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20-May-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add support of STM32MP135 Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
427f452c |
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22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
234b03f3 |
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22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
4382e55c |
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22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
56a368f6 |
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22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
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21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
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21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
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06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
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28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
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09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
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09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
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04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
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21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
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21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
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11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
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24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
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24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
c45973bc |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
778f4eaa |
|
27-Oct-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Add stm32mp2 support Add stm32mp2 compatible. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
1e94b46f |
|
14-Sep-2023 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/printk.h from common header This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bff0d846 |
|
27-Mar-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() For debug purpose, it should be useful to indicate the slew rate for each pins. Add ospeed register information for pins which are configured in either alternate function or gpio output. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
2c38f7c3 |
|
30-Aug-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name Populate uc_priv->name[] with pinmux node's name in order to indicate the pinmuxing's name in case GPIO is configured in alternate. For example, for STM32 SoC's based platform, "gpio status" command output : before Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func GPIOZ5: func GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown After Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func i2c4-0 GPIOZ5: func i2c4-0 GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
cf1d0fd4 |
|
20-May-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add support of STM32MP135 Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
427f452c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
234b03f3 |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
4382e55c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
56a368f6 |
|
22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
778f4eaa |
|
27-Oct-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Add stm32mp2 support Add stm32mp2 compatible. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
1e94b46f |
|
14-Sep-2023 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/printk.h from common header This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bff0d846 |
|
27-Mar-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() For debug purpose, it should be useful to indicate the slew rate for each pins. Add ospeed register information for pins which are configured in either alternate function or gpio output. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
2c38f7c3 |
|
30-Aug-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name Populate uc_priv->name[] with pinmux node's name in order to indicate the pinmuxing's name in case GPIO is configured in alternate. For example, for STM32 SoC's based platform, "gpio status" command output : before Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func GPIOZ5: func GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown After Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func i2c4-0 GPIOZ5: func i2c4-0 GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
cf1d0fd4 |
|
20-May-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add support of STM32MP135 Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
427f452c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
234b03f3 |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
4382e55c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
56a368f6 |
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22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
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06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
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09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1e94b46f |
|
14-Sep-2023 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/printk.h from common header This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bff0d846 |
|
27-Mar-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() For debug purpose, it should be useful to indicate the slew rate for each pins. Add ospeed register information for pins which are configured in either alternate function or gpio output. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
2c38f7c3 |
|
30-Aug-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name Populate uc_priv->name[] with pinmux node's name in order to indicate the pinmuxing's name in case GPIO is configured in alternate. For example, for STM32 SoC's based platform, "gpio status" command output : before Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func GPIOZ5: func GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown After Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func i2c4-0 GPIOZ5: func i2c4-0 GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
cf1d0fd4 |
|
20-May-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add support of STM32MP135 Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
427f452c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
234b03f3 |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
4382e55c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
56a368f6 |
|
22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
bff0d846 |
|
27-Mar-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() For debug purpose, it should be useful to indicate the slew rate for each pins. Add ospeed register information for pins which are configured in either alternate function or gpio output. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
2c38f7c3 |
|
30-Aug-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name Populate uc_priv->name[] with pinmux node's name in order to indicate the pinmuxing's name in case GPIO is configured in alternate. For example, for STM32 SoC's based platform, "gpio status" command output : before Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func GPIOZ5: func GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown After Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func i2c4-0 GPIOZ5: func i2c4-0 GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
cf1d0fd4 |
|
20-May-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add support of STM32MP135 Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
427f452c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
234b03f3 |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
4382e55c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
56a368f6 |
|
22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c38f7c3 |
|
30-Aug-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name Populate uc_priv->name[] with pinmux node's name in order to indicate the pinmuxing's name in case GPIO is configured in alternate. For example, for STM32 SoC's based platform, "gpio status" command output : before Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func GPIOZ5: func GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown After Bank GPIOZ: GPIOZ0: unused : 0 [ ] GPIOZ1: unused : 0 [ ] GPIOZ2: unused : 0 [ ] GPIOZ3: unused : 0 [ ] GPIOZ4: func i2c4-0 GPIOZ5: func i2c4-0 GPIOZ6: unused : 0 [ ] GPIOZ7: unused : 0 [ ] GPIOZ8: unknown GPIOZ9: unknown GPIOZ10: unknown GPIOZ11: unknown GPIOZ12: unknown GPIOZ13: unknown GPIOZ14: unknown GPIOZ15: unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
cf1d0fd4 |
|
20-May-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add support of STM32MP135 Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
427f452c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
234b03f3 |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
4382e55c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
56a368f6 |
|
22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
cf1d0fd4 |
|
20-May-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add support of STM32MP135 Add support for "st,stm32mp135-pinctrl" for STM32MP13x Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
427f452c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
234b03f3 |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
4382e55c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
56a368f6 |
|
22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
427f452c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
gpio: stm32_gpio: Rework GPIO hole management On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank Example: If GPIO bank have 16 GPIO pins [0-15]. In particular SoC's package case, some GPIO bank can have less GPIO pins: - [0-10] => 11 pins; - [2-7] => 6 pins. Commit dbf928dd2634 ("gpio: stm32f7: Add gpio bank holes management") proposed a first implementation by not counting GPIO "inside" hole. GPIO are not displaying correctly using gpio or pinmux command when GPIO holes are located at the beginning of GPIO bank. To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges struct to indicate if a GPIO is mapped or not. GPIO uclass offers several GPIO functions ("input", "output", "unused", "unknown" and "func"), use "unknown" GPIO function to indicate that a GPIO is not mapped. stm32_offset_to_index() is no more needed and removed. This must be reflected using the "gpio" command to indicate to user that a particular GPIO is not mapped (marked as "unknown") as shown below: Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins mapped): GPIOI0 : unknown GPIOI1 : unknown GPIOI2 : analog GPIOI3 : analog GPIOI4 : alt function 0 push-pull pull-down GPIOI5 : alt function 0 push-pull pull-down GPIOI6 : alt function 0 push-pull pull-down GPIOI7 : analog GPIOI8 : unknown GPIOI9 : unknown GPIOI10 : unknown GPIOI11 : unknown GPIOI12 : unknown GPIOI13 : unknown GPIOI14 : unknown GPIOI15 : unknown Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
234b03f3 |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins GPIOF_UNKNOWN becomes a valid pin muxing information to indicate that a pin is not mapped. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
4382e55c |
|
22-Apr-2022 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: Update pinmux_mode definition pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
56a368f6 |
|
22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
56a368f6 |
|
22-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
gpio: stm32: create include file for driver private data The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4363aac0 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: bind only the enabled GPIO subnode Bind only the enabled GPIO subnode, to avoid to probe the node "gpio-controller" present in SOC dtsi (disabled by default) but not enabled in the included pincontrol dtsi file. For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent: gpioj: gpio@5000b000 gpiok: gpio@5000c000 Then these GPIO are absent in output of command "dm tree" and "gpio status -a" Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
1da42691 |
|
21-Jan-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: correct management pin display of OTYPE OTYPE can be used for output or for alternate function to select PP = push-pull or OP = open-drain mode, according reference manual (Table 81. Port bit configuration table). This patch removes this indication for input pins and adds it for AF and output pins for pinmux command output. Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
28b3e7be |
|
06-Nov-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: migrate trace to log macro Change debug to log macro and define LOG_CATEGORY. Remove "%s:" with __func__ as it is managed by log macro (CONFIG_LOGF_FUNC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b305dbc0 |
|
28-Oct-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: display bias information for all pins Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
10bccd0d |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: Add header with SPDX licence Cosmetics: Add header with SPDX licence Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
d3bfad26 |
|
09-Sep-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: Convert to use APIs which support live DT Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
da7a0bb1 |
|
04-Jun-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: add information on pin configuration Add information on pin configuration used for pinmux command: - bias configuration for output (disable, pull up, pull down) - otype for input (open drain or push pull) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d72caa5 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop image.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
73858264 |
|
30-Jul-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: pinctrl_stm32: cosmetic: Reorder include files Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
158abbf5 |
|
21-Jun-2019 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: update .bind callback Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
91ca91e8 |
|
21-Jun-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1 This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
dd18df44 |
|
11-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add st,stm32f769-pinctrl compatible string Due to DT kernel synchronisation, add new pinctrl compatible string for stm32f769. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
530b63c2 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev() Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must be updated. stm32_pinctrl_get_gpio_dev() returns from a given pin selectors the corresponding bank gpio device and the gpio_offset inside this gpio bank. Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
04355041 |
|
03-Dec-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Move gpio_dev list filling outside probe() Move gpio_dev list filling outside probe() to speed-up U-boot boot sequence execution. This list is populated only when needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
075b0185 |
|
27-Nov-2018 |
Benjamin Gaignard <benjamin.gaignard@linaro.org> |
pinctrl: stm32: make pinctrl use hwspinlock Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> |
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> |
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b42d938c |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_muxing() ops Add get_pin_muxing() ops to obtain the pin muxing description a given pin index. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4ff1c20b |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pin_name() ops Add get_pin_name ops to obtain a pin name given a pin index of a specified pin-controller. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
8f651ca6 |
|
24-Oct-2018 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: Add get_pins_count() ops Add get_pins_count ops to obtain the number of pins owns by a pin-controller. On STM32 SoCs bindings, each pin-controller owns several gpio banks. Each GPIO bank can own up to 16 pins. To obtain the total pins count, walk through each sub-nodes (ie GPIO banks) and sum each GPIO banks pins number. For that in probe() we build a list with each GPIO device reference found. This list will also be used with future get_pin_muxing and get_pin_name ops to speed up and optimize walk through all GPIO banks. As this code is common to all STM32 SoCs, this code is put under SPL_BUILD compilation flag to avoid to increase SPL code size for STM32F7 which is limited to 32Ko. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
8aeba629 |
|
12-Mar-2018 |
Patrick Delaunay <patrick.delaunay@st.com> |
pinctrl: stm32: update pincontrol for stmp32mp157 - add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
|
#
98693c22 |
|
12-Dec-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32f4 pinctrl compatible strings STM32F4 SoCs uses the same pinctrl block as found into STM32F7 and H7 SoCs. We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl" compatible string into pinctrl_stm32.c. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
|
#
9b643e31 |
|
15-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: replace with error() with pr_err() U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
092e72cb |
|
13-Sep-2017 |
Patrice Chotard <patrice.chotard@st.com> |
pinctrl: stm32: add stm32h743-pinctrl compatible STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
|
#
bb44b968 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: add set_state ops set_state_ops is kept under PINCTRL_FULL flag in order to decrease memory footprint in some configuration. PINCTRL_FULL can be enabled for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
|
#
ad0376e0 |
|
20-Jun-2017 |
Christophe Kerello <christophe.kerello@st.com> |
pinctrl: stm32: handle a configuration list This patch handles a configuration list behind pinctrl-0 like pinctrl-0 = <&qspi_clk_a &qspi_bk1_a &qspi_bk2_a>; Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
|
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fb3c8d |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: increase the max no of pin configuration to 70 The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
|
#
280057bd |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
stm32f7: use stm32f7 gpio driver supporting driver model With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
77417102 |
|
10-Apr-2017 |
Vikas Manocha <vikas.manocha@st.com> |
dm: gpio: Add driver for stm32f7 gpio controller This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
94d53084 |
|
12-Feb-2017 |
Vikas Manocha <vikas.manocha@st.com> |
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|