#
ecc8d425 |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
fbcb2ff5 |
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27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
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27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
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15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
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27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d18d06ac |
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27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
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24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
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15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
fbcb2ff5 |
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27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d18d06ac |
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27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
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27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
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15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
fbcb2ff5 |
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27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
0205beb1 |
|
15-Oct-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
fbcb2ff5 |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d18d06ac |
|
27-Aug-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
b89e3d92 |
|
24-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
dm: pci: add Freescale PowerPC PCIe driver Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|