#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2bfab76f |
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20-Jan-2024 |
Maksim Kiselev <bigunclemax@gmail.com> |
net: sun8i-emac: Add support for fixed-link phy Make the "phy-handle" property optional, which allows support for a fixed-link phy configuration. Thus if the "phy-handle" is present in a DT, then driver will work as before. Otherwise, phyaddr initialization will not be necessary, as it is not needed in case of a fixed-link config. Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
7b252df7 |
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30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Drop DM_GPIO checks DM_GPIO is always enable in U-Boot proper for ARCH_SUNXI, and this driver is never enabled in SPL, so the condition is always true. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
5ad98c57 |
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08-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: remove CONFIG_MACPWR The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). In the DT this is described with the phy-supply property in the MAC DT node, pointing to a (GPIO controlled) regulator. Since we need Ethernet only in U-Boot proper, and use a DM driver there, we should use the DT instead of hardcoding this. Add code to the sun8i_emac and sunxi_emac drivers to check the DT for that regulator and enable it, at probe time. Then drop the current code from board.c, which was doing that job before. This allows us to remove the MACPWR Kconfig definition and the respective values from the defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> |
#
93f93fe4 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Remove the SoC variant ID Now that all differences in functionality are covered by individual flags, remove the enumeration of SoC variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
3cfb1e69 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Use common syscon setup for R40 While R40 puts the EMAC syscon register at a different address from other variants, the relevant portion of the register's layout is the same. Factor out the register offset so the same code can be shared by all variants. This matches what the Linux driver does. This change provides two benefits beyond the simplification: - R40 boards now respect the RX delays from the devicetree - This resolves a warning on architectures where readl/writel expect the address to have a pointer type, not phys_addr_t. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0e148342 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for the internal PHY switch Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c5ac4b16 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for RMII support Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c86d4732 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a structure for variant data Currently, EMAC variants are distinguished by their identity, but this gets unwieldy as more overlapping variants are added. Add a structure so we can describe the individual feature differences between the variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
68655e6c |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Drop use of arch-specific header This header is not used since commit abdbefba2a4e ("net: sun8i_emac: Use consistent clock bitfield definitions"). Dropping it allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
62ee0433 |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Downgrade printf during probe to debug This just prints the PHY mode taken from the devicetree. It does not need to be printed during every boot, and also avoids an unwanted line break for the "net: " reporting line. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
7f418ea5 |
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15-Apr-2022 |
Tom Rini <trini@konsulko.com> |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net - DM9000 DM support - tftp server bug fix - mdio ofnode support functions - Various phy fixes and improvements. [trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c drivers/net/phy/phy.c include/phy.h]
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#
b638814e |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
bcmgenet, sun8i_emac: Don't connect PHY two times The bcmgenet and sun8i_emac drivers call phy_connect(), which finds / creates the PHY and also connects it to the eth device via phy_connect_dev(), then set some phydev members (bcmgenet only), and then call phy_connect_dev() explicitly again. Drop the second phy_connect_dev(), since it is unnecesary. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
ffb0f6f4 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
123ca114 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
net: introduce helpers to get PHY interface mode from a device/ofnode Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the "phy-mode" / "phy-connection-type" property. Add corresponding UT test. Use them treewide. This allows us to inline the phy_get_interface_by_name() into ofnode_read_phy_mode(), since the former is not used anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
|
11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
2bfab76f |
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20-Jan-2024 |
Maksim Kiselev <bigunclemax@gmail.com> |
net: sun8i-emac: Add support for fixed-link phy Make the "phy-handle" property optional, which allows support for a fixed-link phy configuration. Thus if the "phy-handle" is present in a DT, then driver will work as before. Otherwise, phyaddr initialization will not be necessary, as it is not needed in case of a fixed-link config. Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
7b252df7 |
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30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Drop DM_GPIO checks DM_GPIO is always enable in U-Boot proper for ARCH_SUNXI, and this driver is never enabled in SPL, so the condition is always true. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
5ad98c57 |
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08-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: remove CONFIG_MACPWR The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). In the DT this is described with the phy-supply property in the MAC DT node, pointing to a (GPIO controlled) regulator. Since we need Ethernet only in U-Boot proper, and use a DM driver there, we should use the DT instead of hardcoding this. Add code to the sun8i_emac and sunxi_emac drivers to check the DT for that regulator and enable it, at probe time. Then drop the current code from board.c, which was doing that job before. This allows us to remove the MACPWR Kconfig definition and the respective values from the defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> |
#
93f93fe4 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Remove the SoC variant ID Now that all differences in functionality are covered by individual flags, remove the enumeration of SoC variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
3cfb1e69 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Use common syscon setup for R40 While R40 puts the EMAC syscon register at a different address from other variants, the relevant portion of the register's layout is the same. Factor out the register offset so the same code can be shared by all variants. This matches what the Linux driver does. This change provides two benefits beyond the simplification: - R40 boards now respect the RX delays from the devicetree - This resolves a warning on architectures where readl/writel expect the address to have a pointer type, not phys_addr_t. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0e148342 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for the internal PHY switch Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c5ac4b16 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for RMII support Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c86d4732 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a structure for variant data Currently, EMAC variants are distinguished by their identity, but this gets unwieldy as more overlapping variants are added. Add a structure so we can describe the individual feature differences between the variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
68655e6c |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Drop use of arch-specific header This header is not used since commit abdbefba2a4e ("net: sun8i_emac: Use consistent clock bitfield definitions"). Dropping it allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
62ee0433 |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Downgrade printf during probe to debug This just prints the PHY mode taken from the devicetree. It does not need to be printed during every boot, and also avoids an unwanted line break for the "net: " reporting line. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
7f418ea5 |
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15-Apr-2022 |
Tom Rini <trini@konsulko.com> |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net - DM9000 DM support - tftp server bug fix - mdio ofnode support functions - Various phy fixes and improvements. [trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c drivers/net/phy/phy.c include/phy.h]
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#
b638814e |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
bcmgenet, sun8i_emac: Don't connect PHY two times The bcmgenet and sun8i_emac drivers call phy_connect(), which finds / creates the PHY and also connects it to the eth device via phy_connect_dev(), then set some phydev members (bcmgenet only), and then call phy_connect_dev() explicitly again. Drop the second phy_connect_dev(), since it is unnecesary. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
ffb0f6f4 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
123ca114 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
net: introduce helpers to get PHY interface mode from a device/ofnode Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the "phy-mode" / "phy-connection-type" property. Add corresponding UT test. Use them treewide. This allows us to inline the phy_get_interface_by_name() into ofnode_read_phy_mode(), since the former is not used anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
7b252df7 |
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30-Oct-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Drop DM_GPIO checks DM_GPIO is always enable in U-Boot proper for ARCH_SUNXI, and this driver is never enabled in SPL, so the condition is always true. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
5ad98c57 |
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08-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: remove CONFIG_MACPWR The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). In the DT this is described with the phy-supply property in the MAC DT node, pointing to a (GPIO controlled) regulator. Since we need Ethernet only in U-Boot proper, and use a DM driver there, we should use the DT instead of hardcoding this. Add code to the sun8i_emac and sunxi_emac drivers to check the DT for that regulator and enable it, at probe time. Then drop the current code from board.c, which was doing that job before. This allows us to remove the MACPWR Kconfig definition and the respective values from the defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> |
#
93f93fe4 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Remove the SoC variant ID Now that all differences in functionality are covered by individual flags, remove the enumeration of SoC variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
3cfb1e69 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Use common syscon setup for R40 While R40 puts the EMAC syscon register at a different address from other variants, the relevant portion of the register's layout is the same. Factor out the register offset so the same code can be shared by all variants. This matches what the Linux driver does. This change provides two benefits beyond the simplification: - R40 boards now respect the RX delays from the devicetree - This resolves a warning on architectures where readl/writel expect the address to have a pointer type, not phys_addr_t. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0e148342 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for the internal PHY switch Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c5ac4b16 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for RMII support Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c86d4732 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a structure for variant data Currently, EMAC variants are distinguished by their identity, but this gets unwieldy as more overlapping variants are added. Add a structure so we can describe the individual feature differences between the variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
68655e6c |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Drop use of arch-specific header This header is not used since commit abdbefba2a4e ("net: sun8i_emac: Use consistent clock bitfield definitions"). Dropping it allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
62ee0433 |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Downgrade printf during probe to debug This just prints the PHY mode taken from the devicetree. It does not need to be printed during every boot, and also avoids an unwanted line break for the "net: " reporting line. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
7f418ea5 |
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15-Apr-2022 |
Tom Rini <trini@konsulko.com> |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net - DM9000 DM support - tftp server bug fix - mdio ofnode support functions - Various phy fixes and improvements. [trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c drivers/net/phy/phy.c include/phy.h]
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#
b638814e |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
bcmgenet, sun8i_emac: Don't connect PHY two times The bcmgenet and sun8i_emac drivers call phy_connect(), which finds / creates the PHY and also connects it to the eth device via phy_connect_dev(), then set some phydev members (bcmgenet only), and then call phy_connect_dev() explicitly again. Drop the second phy_connect_dev(), since it is unnecesary. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
ffb0f6f4 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
123ca114 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
net: introduce helpers to get PHY interface mode from a device/ofnode Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the "phy-mode" / "phy-connection-type" property. Add corresponding UT test. Use them treewide. This allows us to inline the phy_get_interface_by_name() into ofnode_read_phy_mode(), since the former is not used anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
5ad98c57 |
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08-Jun-2022 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: remove CONFIG_MACPWR The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). In the DT this is described with the phy-supply property in the MAC DT node, pointing to a (GPIO controlled) regulator. Since we need Ethernet only in U-Boot proper, and use a DM driver there, we should use the DT instead of hardcoding this. Add code to the sun8i_emac and sunxi_emac drivers to check the DT for that regulator and enable it, at probe time. Then drop the current code from board.c, which was doing that job before. This allows us to remove the MACPWR Kconfig definition and the respective values from the defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> |
#
93f93fe4 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Remove the SoC variant ID Now that all differences in functionality are covered by individual flags, remove the enumeration of SoC variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
3cfb1e69 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Use common syscon setup for R40 While R40 puts the EMAC syscon register at a different address from other variants, the relevant portion of the register's layout is the same. Factor out the register offset so the same code can be shared by all variants. This matches what the Linux driver does. This change provides two benefits beyond the simplification: - R40 boards now respect the RX delays from the devicetree - This resolves a warning on architectures where readl/writel expect the address to have a pointer type, not phys_addr_t. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0e148342 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for the internal PHY switch Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c5ac4b16 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for RMII support Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c86d4732 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a structure for variant data Currently, EMAC variants are distinguished by their identity, but this gets unwieldy as more overlapping variants are added. Add a structure so we can describe the individual feature differences between the variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
68655e6c |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Drop use of arch-specific header This header is not used since commit abdbefba2a4e ("net: sun8i_emac: Use consistent clock bitfield definitions"). Dropping it allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
62ee0433 |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Downgrade printf during probe to debug This just prints the PHY mode taken from the devicetree. It does not need to be printed during every boot, and also avoids an unwanted line break for the "net: " reporting line. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
7f418ea5 |
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15-Apr-2022 |
Tom Rini <trini@konsulko.com> |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net - DM9000 DM support - tftp server bug fix - mdio ofnode support functions - Various phy fixes and improvements. [trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c drivers/net/phy/phy.c include/phy.h]
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#
b638814e |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
bcmgenet, sun8i_emac: Don't connect PHY two times The bcmgenet and sun8i_emac drivers call phy_connect(), which finds / creates the PHY and also connects it to the eth device via phy_connect_dev(), then set some phydev members (bcmgenet only), and then call phy_connect_dev() explicitly again. Drop the second phy_connect_dev(), since it is unnecesary. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
ffb0f6f4 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
123ca114 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
net: introduce helpers to get PHY interface mode from a device/ofnode Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the "phy-mode" / "phy-connection-type" property. Add corresponding UT test. Use them treewide. This allows us to inline the phy_get_interface_by_name() into ofnode_read_phy_mode(), since the former is not used anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
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b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
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219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
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caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <masahiroy@kernel.org> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
93f93fe4 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Remove the SoC variant ID Now that all differences in functionality are covered by individual flags, remove the enumeration of SoC variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
3cfb1e69 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Use common syscon setup for R40 While R40 puts the EMAC syscon register at a different address from other variants, the relevant portion of the register's layout is the same. Factor out the register offset so the same code can be shared by all variants. This matches what the Linux driver does. This change provides two benefits beyond the simplification: - R40 boards now respect the RX delays from the devicetree - This resolves a warning on architectures where readl/writel expect the address to have a pointer type, not phys_addr_t. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0e148342 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for the internal PHY switch Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c5ac4b16 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a flag for RMII support Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
c86d4732 |
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22-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Add a structure for variant data Currently, EMAC variants are distinguished by their identity, but this gets unwieldy as more overlapping variants are added. Add a structure so we can describe the individual feature differences between the variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
68655e6c |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Drop use of arch-specific header This header is not used since commit abdbefba2a4e ("net: sun8i_emac: Use consistent clock bitfield definitions"). Dropping it allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
62ee0433 |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Downgrade printf during probe to debug This just prints the PHY mode taken from the devicetree. It does not need to be printed during every boot, and also avoids an unwanted line break for the "net: " reporting line. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
7f418ea5 |
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15-Apr-2022 |
Tom Rini <trini@konsulko.com> |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net - DM9000 DM support - tftp server bug fix - mdio ofnode support functions - Various phy fixes and improvements. [trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c drivers/net/phy/phy.c include/phy.h]
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#
b638814e |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
bcmgenet, sun8i_emac: Don't connect PHY two times The bcmgenet and sun8i_emac drivers call phy_connect(), which finds / creates the PHY and also connects it to the eth device via phy_connect_dev(), then set some phydev members (bcmgenet only), and then call phy_connect_dev() explicitly again. Drop the second phy_connect_dev(), since it is unnecesary. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
ffb0f6f4 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
123ca114 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
net: introduce helpers to get PHY interface mode from a device/ofnode Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the "phy-mode" / "phy-connection-type" property. Add corresponding UT test. Use them treewide. This allows us to inline the phy_get_interface_by_name() into ofnode_read_phy_mode(), since the former is not used anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
|
22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
|
03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
|
03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
|
15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
6e7df1d1 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
68655e6c |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Drop use of arch-specific header This header is not used since commit abdbefba2a4e ("net: sun8i_emac: Use consistent clock bitfield definitions"). Dropping it allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
62ee0433 |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Downgrade printf during probe to debug This just prints the PHY mode taken from the devicetree. It does not need to be printed during every boot, and also avoids an unwanted line break for the "net: " reporting line. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
7f418ea5 |
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15-Apr-2022 |
Tom Rini <trini@konsulko.com> |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net - DM9000 DM support - tftp server bug fix - mdio ofnode support functions - Various phy fixes and improvements. [trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c drivers/net/phy/phy.c include/phy.h]
|
#
b638814e |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
bcmgenet, sun8i_emac: Don't connect PHY two times The bcmgenet and sun8i_emac drivers call phy_connect(), which finds / creates the PHY and also connects it to the eth device via phy_connect_dev(), then set some phydev members (bcmgenet only), and then call phy_connect_dev() explicitly again. Drop the second phy_connect_dev(), since it is unnecesary. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
ffb0f6f4 |
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06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
123ca114 |
|
06-Apr-2022 |
Marek Behún <kabel@kernel.org> |
net: introduce helpers to get PHY interface mode from a device/ofnode Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the "phy-mode" / "phy-connection-type" property. Add corresponding UT test. Use them treewide. This allows us to inline the phy_get_interface_by_name() into ofnode_read_phy_mode(), since the former is not used anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
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d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
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2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68655e6c |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Drop use of arch-specific header This header is not used since commit abdbefba2a4e ("net: sun8i_emac: Use consistent clock bitfield definitions"). Dropping it allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
62ee0433 |
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14-Jul-2022 |
Samuel Holland <samuel@sholland.org> |
net: sun8i-emac: Downgrade printf during probe to debug This just prints the PHY mode taken from the devicetree. It does not need to be printed during every boot, and also avoids an unwanted line break for the "net: " reporting line. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
7f418ea5 |
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15-Apr-2022 |
Tom Rini <trini@konsulko.com> |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net - DM9000 DM support - tftp server bug fix - mdio ofnode support functions - Various phy fixes and improvements. [trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c drivers/net/phy/phy.c include/phy.h]
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#
b638814e |
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06-Apr-2022 |
Marek Behún <marek.behun@nic.cz> |
bcmgenet, sun8i_emac: Don't connect PHY two times The bcmgenet and sun8i_emac drivers call phy_connect(), which finds / creates the PHY and also connects it to the eth device via phy_connect_dev(), then set some phydev members (bcmgenet only), and then call phy_connect_dev() explicitly again. Drop the second phy_connect_dev(), since it is unnecesary. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
ffb0f6f4 |
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06-Apr-2022 |
Marek Behún <marek.behun@nic.cz> |
treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
123ca114 |
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06-Apr-2022 |
Marek Behún <marek.behun@nic.cz> |
net: introduce helpers to get PHY interface mode from a device/ofnode Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the "phy-mode" / "phy-connection-type" property. Add corresponding UT test. Use them treewide. This allows us to inline the phy_get_interface_by_name() into ofnode_read_phy_mode(), since the former is not used anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
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2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
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4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
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a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
7f418ea5 |
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15-Apr-2022 |
Tom Rini <trini@konsulko.com> |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net - DM9000 DM support - tftp server bug fix - mdio ofnode support functions - Various phy fixes and improvements. [trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c drivers/net/phy/phy.c include/phy.h]
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#
b638814e |
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06-Apr-2022 |
Marek Behún <marek.behun@nic.cz> |
bcmgenet, sun8i_emac: Don't connect PHY two times The bcmgenet and sun8i_emac drivers call phy_connect(), which finds / creates the PHY and also connects it to the eth device via phy_connect_dev(), then set some phydev members (bcmgenet only), and then call phy_connect_dev() explicitly again. Drop the second phy_connect_dev(), since it is unnecesary. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
ffb0f6f4 |
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06-Apr-2022 |
Marek Behún <marek.behun@nic.cz> |
treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
#
123ca114 |
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06-Apr-2022 |
Marek Behún <marek.behun@nic.cz> |
net: introduce helpers to get PHY interface mode from a device/ofnode Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the "phy-mode" / "phy-connection-type" property. Add corresponding UT test. Use them treewide. This allows us to inline the phy_get_interface_by_name() into ofnode_read_phy_mode(), since the former is not used anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
|
22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
ae022e83 |
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28-Aug-2021 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Remove non-DM pin setup This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
|
03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
|
11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
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caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
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41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
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2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
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60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
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d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
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2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
42508461 |
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11-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
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2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
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d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
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2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
02036d90 |
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03-Jun-2021 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
net: sun8i-emac: fix MDIO frequency Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
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401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
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eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
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b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
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219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
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d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
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caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
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41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
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2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
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60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
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d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
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9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
4e26bc63 |
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15-Apr-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Fix pinmux setup for Allwinner H5 Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
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2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
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4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
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a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
|
22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
|
06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
401d1c4f |
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30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
|
11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
|
21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
|
21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
|
15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
|
07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
|
19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
eb5a2b67 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Determine pinmux based on SoC, not EMAC type The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
b14e5205 |
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11-Jan-2021 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Always clear syscon EPHY register At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
219a5d5a |
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14-Nov-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Allow all RGMII PHY modes So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
|
05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
|
22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
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4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
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a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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d1998a9f |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c69cda25 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename dev_get_platdata() to dev_get_plat() Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org> |
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caa4daa2 |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
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41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
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2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
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60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
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d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
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9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
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2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
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4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
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a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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4f0278da |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Lower MDIO frequency When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
88ae8fba |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Make internal PHY handling more robust The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
7edcb4e2 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify and fix error handling for RX The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2c5600c3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix MAC soft reset The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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09501ff3 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Fix overlong lines When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
8c274ec0 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Wrap and simplify cache maintenance operations To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
eaeadb50 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Drop unneeded cache invalidation before sending There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ed909de5 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Reduce cache maintenance on TX descriptor init When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
69853123 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Improve cache maintenance on RX descriptor init Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
4fe86412 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Name magic bits and simplify read-modify-write calls The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
a5b2a991 |
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21-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Remove pointless wrapper functions Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
f20f9465 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Simplify mdio_read/mdio_write functions When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
c35380c7 |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i_emac: Don't hand out TX descriptor too early When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
2808cf6c |
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05-Jul-2020 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: Bail out on PHY error When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
ef043693 |
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15-Sep-2020 |
Sean Anderson <seanga2@gmail.com> |
net: sun8i_emac: Fix not calling dev_xxx with a device Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
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4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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2548493a |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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7208396b |
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24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
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60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
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cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
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336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
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d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
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9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
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2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
7208396b |
|
24-Jul-2020 |
Tom Rini <trini@konsulko.com> |
Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com> |
#
60e7fa8b |
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16-Jul-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
treewide: convert devfdt_get_addr() to dev_read_addr() When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
99ac8618 |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
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07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
|
03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
|
22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
|
06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
99ac8618 |
|
07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Add support for the H6 variant The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
abdbefba |
|
07-May-2020 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Use consistent clock bitfield definitions While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
90526e9f |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
|
19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
|
22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
cd93d625 |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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90526e9f |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
|
03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
|
03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
|
22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
|
22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
336d4615 |
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03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
|
19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
|
22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
|
03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
|
27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
|
22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
|
22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
|
15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
|
17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
|
15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
|
17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
|
27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
bcee8d67 |
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06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: gpio: Allow control of GPIO uclass in SPL At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
1eb69ae4 |
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14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
|
22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
|
03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
|
17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
|
15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
#
a85ba87d |
|
22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
68728448 |
|
22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
|
06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1eb69ae4 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move ARM cache operations out of common.h These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d53e5222 |
|
19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
2348453c |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
|
27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
|
22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
e46d73fa |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
|
13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
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a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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d53e5222 |
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19-Jul-2019 |
Emmanuel Vadot <manu@freebsd.org> |
net: sun8i_emac: Test the correct phy H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
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2348453c |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
d3a2c058 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Add CLK and RESET support Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> |
#
695f6043 |
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27-Feb-2019 |
Jagan Teki <jagan@amarulasolutions.com> |
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> |
#
9b16ede4 |
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22-Nov-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sun8i_emac: add support for setting EMAC TX/RX delay Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> |
#
2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com> |
#
7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
#
e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com> |
#
6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> |
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org> |
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4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> |
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a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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e46d73fa |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: support R40 GMAC Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
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c6a21d66 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: set mux and clock by driver data Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
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2f157436 |
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13-Jul-2018 |
Lothar Felten <lothar.felten@gmail.com> |
net: sun8i-emac: fix printing NULL character If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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ecd0cec0 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: remove support for old binding The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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12afd957 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: add support for new EMAC DT binding The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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c0341173 |
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03-Apr-2018 |
Andre Przywara <andre.przywara@arm.com> |
net: sun8i-emac: support new pinctrl DT bindings The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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2d53018a |
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27-Jan-2018 |
Samuel Holland <samuel@sholland.org> |
net: sun8i_emac: Fix PHY initialization The previous code tried to update the PHY parameters without waiting for autonegotiation to complete. This caused wrong values to be written to the EMAC in sun8i_adjust_link(). As a result, any commands that called eth_start() before autonegotiation completed would find the network nonfunctional. Fix this by using the correct function to start up the PHY. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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13ae2a40 |
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22-Sep-2017 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Fix build for non-H3/H5 SoCs Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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da409ccc |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor (part 2) At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
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a821c4af |
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17-May-2017 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_addr..() functions These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
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4d555ae3 |
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22-Feb-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: configure PHY reset GPIO via DM This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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7b82a229 |
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15-Feb-2017 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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e160f7d4 |
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17-Jan-2017 |
Simon Glass <sjg@chromium.org> |
dm: core: Replace of_offset with accessor At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
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1deeecb6 |
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15-Nov-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sun8i_emac: Fix mdio read sequence To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
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6e67f176 |
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17-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Fix codying style broken by recent libfdt sync Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
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b02e4044 |
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02-Oct-2016 |
Simon Glass <sjg@chromium.org> |
libfdt: Bring in upstream stringlist functions These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org>
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#
4069437d |
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27-Jul-2016 |
Hans de Goede <hdegoede@redhat.com> |
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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#
a85ba87d |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Drop redundant and incorrect setting of syscon register In sun8i_emac_board_setup, the driver partially configures the syscon register for H3 EPHY. However, the settings are incomplete, and completely unusable. The correct settings are later set in sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists. It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not have a 25 MHz clock the EPHY can use. This patch removes the setting of the syscon register in board_setup, and also moves set_syscon above mdio_init. While mdio_init does not access the PHY, it is better to have the PHY parameters setup before the MDIO bus is registered. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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#
68728448 |
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22-Jul-2016 |
Chen-Yu Tsai <wens@csie.org> |
net: sun8i_emac: Do not configure AHB2 clock The sun8i_emac driver erroneously configures the AHB2 clock when it assumes it is configuring the AXI gates, which is not even documented or ever appeared in either the WiP kernel driver or Allwinner's original driver. As a result, AHB2 clock mux is set to an invalid setting, making the EPHY unusable. Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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a29710c5 |
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06-Jul-2016 |
Amit Singh Tomar <amittomer25@gmail.com> |
net: Add EMAC driver for H3/A83T/A64 SoCs. This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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